A Pixel array of an LCD panel includes a plurality of interleaving row gate lines and column data lines; wherein, the driving of the gate lines can be implemented by an attached integrated driving circuit, and thus it needs to reserve certain areas at the edge of the array substrate of the LCD panel as a bonding area of the integrated driving circuit and a fan-out wiring area for gate lines on the array substrate. Then the integrated driving circuit can be bonded on the array substrate by a flexible printed circuit board COF (Chip on FPC).
It is known that, when gate lines are driven with the integrated driving circuit, two sides of the LCD panel are designed asymmetric because of the need of certain areas reservation at the edge of the array substrate. Further, the bonding operation causes negative effects on production capacity and yield rate. Therefore, an apparatus for driving gate lines (including a plurality of shifting registers in serial) can be integrated on the array substrate with GOA (Gate Driving on Array) technology to realize symmetric design of the LCD panel and high production capacity and yield rate.
Currently, a typical shifting register utilizing GOA technology generally includes 4 thin film transistors and a capacitor. FIG. 1 is the schematic diagram of such shifting register, and FIG. 2 is the input and output timing chart of the shifting register as shown in FIG. 1. In combination with FIGS. 1 and 2, it can be seen that the working procedure of the shifting register is as follows with selecting 5 phases of T1 to T5 in FIG. 2: at phase T1, a signal input terminal Input is at high level, a clock signal terminal is at low level, and a reset signal terminal Reset is at low level; at this point, a thin film transistor M1 turns on to charge a capacitor C1, and a thin film transistor M3 turns off so that a low level is output at a signal output terminal Output. At phase T2, the signal input terminal Input is at low level, the clock signal terminal is at high level, and the reset signal terminal Reset is at low level; at this point, the bootstrapping effect of the capacitor C1 further pulls up the gate level of the thin film transistor M3, and the thin film transistor M3 turns on, and the signal output terminal Output outputs a pulse of the clock signal terminal, namely, a high level. At phase T3, the signal input terminal Input is at low level, the clock signal terminal is at low level, and the reset signal terminal is at high level; at this point, thin film transistors M2 and M4 turn on, pulling gate level of the thin film transistor M3 and the level of the signal output terminal Output down to a low level Vss. At phase T4, the signal input terminal Input is at low level, the clock signal terminal is at high level, and the reset signal terminal is at low level; at this point, the thin film transistors M1 to M4 are all off, and the signal output terminal Output outputs a low level. At phase T5, the signal input terminal Input is at low level, the clock signal terminal is at low level, and the reset signal terminal is at low level; at this point, the thin film transistors M1 to M4 are all off, and the signal output terminal Output outputs a low level. Thereafter until next time the signal input terminal Input is at high level, the shifting register repeats phases T4 and T5, during which it can be referred as the non-working period of the shifting register.
It can be seen from the working procedure of the shifting register as above that, the gate of the thin film transistor M3 and the signal output terminal Output are in floating state during the non-working period of the shifting register, and when the clock signal terminal is at high level, a parasitic capacitance of the thin film transistor M3 may cause the leak current thereof to increase, and therefore incurs noise to the signal output terminal Output, leading it to output a high level in error.